Bounding DMA Interference on Hard-Real-Time Embedded Systems

Bounding the Execution Times of DMA I/O Tasks on Hard-Real-Time Embedded Systems

Timing Analysis for DAG-based and GFP Scheduled Tasks

Modern embedded systems have made the transition from single-core to multi-core architectures, providing performance improvement via parallelism rather than higher clock frequencies. DAGs are considered among the most generic task models in the real-time domain and are well suited to exploit this parallelism. In this paper we provide a schedulability test using response-time analysis exploiting...

Compositional Verification of Real-Time Fault-Tolerant Programs

A hard-masking real-time program is one that satisfies safety (including timing constraints) and liveness properties in the absence and presence of faults. It has been shown that any hard-masking program can be decomposed into a faultintolerant version and a set of fault-tolerance components known as detectors and δ-correctors. In this paper, we introduce a set of sufficient conditions for inte...

ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts

SUMMARY The unpredictable behavior of cache memory makes it difficult to statically analyze the worst-case performance of real-time systems. This problem is further exacerbated in the case of preemptive multitask systems because of inter-task cache interference, called Cache-Related Pre-emption Delay (CRPD). This paper proposes an approach to analyzing the tight upper bound on CRPD which a task...

A Network Interface Card Architecture for I/O Virtualization in Embedded Systems

In this paper we present an architectural concept for network interface cards (NIC) targeting embedded systems and supporting I/O virtualization. Current solutions for high performance computing do not sufficiently address embedded system requirements i.e., guarantee real-time constraints and differentiated service levels as well as only utilize limited HW resources. The central ideas of our wo...